- RISCOS
Cloe v3 additions
This is a 'living' document. It will contain changes to the Cloe v3 system, mainly optimisations.
- Addition of
ORRxx{S} pc,lr,#1<<n
to branch into Cloe module, where <n> is 28-31. This optimises exit from routines such asORRS pc,lr,#1<<28
, where the routine exits by setting (or clearing - see below) a flag in the status register. - Addition of
BICxx{S} pc,lr,#1<<n
to branch into Cloe module, where <n> is 28-31. This is the same as the above, except it clears a processor status flag. - Translation of
BIC rn,pc,#&fc000003
toMOV rn,pc
. - Translation of
NV
instructions toMOV r0,r0
. - Checking of code such as :
TEQ r0,#0
BEQ is_zero
BNE not_zero
ie. code which does a branch if one condition, followed by a branch if the other condition. This would prevent code which does this to cause problems when Cloe does the conditional check - earlier, Cloe would convert the instructions afterwards.
Date last modified:
2019-10-19 17:11:02