XilMezzie - Schematic

I've been using Eagle PCB for quite a while now, and last year I bought the professional version (mainly because it allows a practically unlimited board size). I've now done a couple of small commercial PCBs with it, but most of the work I do is still personal.

You can download a PDF of the schematic here. It has 7 sheets, all of which are fairly simple.

Xilinx organisation

The FPGA is organised as 4 banks of I/O pins - each having roughly the same number (about 14). Bank 2 has extra pins, and it is involved with the configuration of the device.

There are quite a few clock pins - although banks 1 and 3 are less useful than banks 0 and 2 (well, Xilinx ISE warns you about using them). These pins can become I/O pins if you don't need them to be a clock.

Because of the orientation of the device, I decided that I would use banks 1 and 3 for most of the I/O pins (any input only pins are unused), with the rest being taken from bank 0. This would make tracking fairly easy.

Page 1

Page 1 of the schematic is bank 0. It simply presents all the pins as a netlist, with the wire name being the name of the pin. It also has the 50MHz clock, and also a 10K pull-down resistor for the HSWAP pin (this does become one of the 38 I/O pins).

Page 2

Page 2 is bank 1, and has pretty much the same structure as bank 0. Note that each of the banks have their own VCCO pins, although I've set them to be 3.3V. They also have the smoothing capacitors on the pages.

Page 3

This page is for bank 2, the configuration device and the reset device (which is a positive reset, of 350ms). An additional smoothing capacitor has been added for the configuration FLASH.

Page 4

This makes up the last bank (bank 3), and is very similar to page 2 (bank 1).

Page 5

Page 5 has the AUX and INT voltage lines, the DONE signal LED and also the JTAG interface.

Page 6

Page 6 is the voltage generation. The capacitor values of 4µ7 are the notional values, and I wanted to get a small capacitor with the largest value (I used 22µF tantalum capacitors, size A).

Page 7

Page 7 is how all the pins are wired to the main board. I designed a package for this mezzanine board while laying out the PCB, so when I come to use the board in other projects, I know exactly which pin on the FPGA is being used for what. There should be no ambiguity.

Organising the design

Broadly speaking, the rules for which pin is used where depends on a number of factors:

1. The proximity of the FPGA's pin to the connector's pin
2. Input only pins are ignored
3. Pins which have other purposes are ignored (the exception to this is the HSWAP pin, which unfortunately was in a position where it couldn't be ignored).

I started with the pin most clockwise on bank 1, and connected that to pin 19, and worked anti-clockwise. For the other side, it was the pin most antic-lockwise on bank 2 conected to pin 39, and worked my way clockwise. Any connector pins left out at the end were connected to those in bank 0.

These then defined where the FPGA was in relation to the pins (although the location of the JTAG, power and configuration chip also dictated that).

Eagle PCB symbol

The symbol was divided into groups for which bank they're in, and those that could be used as clocks were marked as clocks. Note that only piuns 1, 2 and 3 are connected to GCLKs; the others are LHCLKs or RHCLKs.

Notes

1. The pin numbering is not the same as a chip (which counts clockwise). This is semi-deliberate (in that I have an excuse - it's not a chip).
2. I have precluded the use of the VREF pins for low-voltage on banks 0 and 1 (and also 2, for that matter). The chances of me having to deal with low-voltage logic is fairly slim at this moment in time (I've only been using 3.3V for about a year!). I would also need to make VCCIOn configurable somehow.